1. Field of the Invention
The present invention generally relates to systems for processing substrates. Specifically, the present invention relates to methods and apparatuses for performing capacitance-voltage measurements on a substrate processed in a processing system.
2. Background of the Related Art
Processing systems for processing 100 mm, 200 mm, 300 mm or other diameter substrates are generally known. Typically, such processing systems have a centralized transfer chamber mounted on a monolith platform. The transfer chamber is the center of activity for the movement of substrates being processed in the system. One or more process chambers mount on the transfer chamber for performing processes on the substrates. Access to the transfer chamber from the clean ambient environment is typically through one or more load lock chambers. A transfer chamber substrate handler is pivotably mounted in the middle of the transfer chamber and can access each of the process chambers and load lock chambers to transfer substrates therebetween. The load lock chambers may open to a very clean room, referred to as the white area, or to a substrate handling chamber, typically referred to as a mini-environment. A substrate handler in the optional mini-environment transfers substrates in a very clean environment at atmospheric pressure from pods, or cassettes or carriers, seated on pod loaders to the load lock chambers.
Several different types of process chambers, such as physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, etch chambers and others, may be attached to the transfer chamber for processing substrates. A PVD chamber, for example, deposits a metal film, such as aluminum or copper, onto the surface of the substrates to form conductive traces connecting various elements, such as transistors and capacitors, of a circuit being created on the substrate. Typically, an insulating layer, such as an oxide, is formed on the surface of the substrate to prevent the metal from contacting at improper locations and vias, or holes, are formed in the insulating layer to permit the metal to contact the proper locations. After the metal is deposited, typically, regions of the metal may be removed, such as by etching, to create individual traces connecting parts of the substrate. To do the deposition, the PVD chamber includes a target of the metal or a compound of the metal displaced opposite a substrate to provide the metal, which will be sputtered onto the substrate. The PVD chamber generates a plasma of a process gas, such as argon, between the target and the substrate. Ions in the plasma are accelerated toward the target to knock the target material loose, so the target material can deposit on the substrate.
A problem with the targets is that a poor quality of material will result in a poor quality of film deposited on the substrate. For example, if the target is contaminated with sodium, then the sodium will deposit onto the substrate surface along with the metal and migrate into the substrate material, thereby causing a short between the semiconductive material of the substrate and the deposited metal film. On the other hand, if the target material is of a good quality, then the metal film and semiconductive substrate will be properly insulated from each other by the oxide layer. In other words, the metal film and the semiconductive substrate will have an expected capacitance between them, with the oxide layer as a dielectric material.
Another problem is that a poor quality of the insulating oxide layer may cause the oxide to have unacceptable insulating capability. The oxide layer is typically formed in a finance, or other device, so if the furnace is not functioning properly, then the oxide layer may be contaminated or, otherwise, of low quality.
Since the metal film, oxide layer and semiconductive substrate form a capacitor, the quality of the target material or the oxide layer or the functioning of the furnace can be determined by a capacitance-voltage test, wherein the capacitance between the metal film and the semiconductive substrate is measured with respect to a voltage applied therebetween. Such a test is typically performed to qualify a target when the target is first placed in the PVD chamber prior to processing substrates or to re-qualify the target after the PVD chamber has been opened or to qualify the furnace. To perform the test, the target material is deposited onto the surface of an exemplary substrate, having the oxide layer at its surface, at a sufficient number of locations to provide reliable data. The target material is deposited at select locations by placing a mask, such as the mask 10 shown in FIG. 1a, onto the substrate 12, and depositing the target material onto the substrate 12 so that the mask prevents deposition except at the holes 16. A pattern of target material will be formed on the substrate 12 at the locations of the holes 16. Afterwards, capacitance-voltage measurements are made at each of the locations of the target material.
The mask 10 is held in place on the substrate 12 by clamps 14, so the substrate 12 can be inserted into the processing system and the PVD chamber, in the same manner as a substrate that is to be processed, without a risk that the mask 10 may slide or fall off of the substrate 12. The PVD chamber has a clamp ring 18 (FIG. 1b) that seats on the periphery of the substrate 12 during deposition of the target material to prevent the plasma of the process gas and the sputtered metal from the target material from leaking out beyond the substrate 12 and contaminating other surfaces of the substrate or depositing onto surfaces of the PVD chamber. A problem with using the mask 10 in a PVD chamber having the clamp ring 18 is that a gap 20 can form between the mask 10 and the clamp ring 18, thereby allowing the plasma and the sputtered material to escape into other parts of the PVD chamber.
A full face mask is one that covers the edge of the test substrate around the entire periphery of the test substrate and can reduce or eliminate the gaps between the clamp ring and the test substrate by providing a surface on which the clamp ring can rest throughout the periphery of the test substrate. However, a problem with a full face mask, that has heretofore made it impractical to use a full face mask, is that the thickness of the test substrate combined with the full face mask is such that the test substrate/mask assembly cannot properly fit into a cassette for delivery to the processing system. The cassettes used for delivering substrates to processing systems are defined by industry standards to have a certain number of teeth, typically about 13 or 25, for supporting the substrates and a certain space between the teeth to provide a needed clearance tolerance for substrates to be placed into and removed from the cassettes. The full face mask must be thick enough to have sufficient strength, but the ideal thickness of the full face mask makes the test substrate/mask assembly too large for adequate clearance tolerances in the space between the shelves of the cassettes. Thus, there is an unacceptable risk of collision between the test substrate/mask assembly and the teeth of the cassettes.
Therefore, a need exists for a mask for performing capacitance-voltage measurements whereby little or no plasma or sputtered material can escape from the region within which the deposition is being performed on the substrate.